Features		Benefits
Package	FBGA	Enables better electrical performance and speed
Voltage	1.55V, 1.8V	Reduces memory system power demand
Densities	256Mb to 4Gb	High-density components enable large memory subsystems
Internal Banks	4 and 8	1Gb and higher DDR2 devices have 8 banks for better performance
Prefetch (MIN WRITE burst)	4	Provides reduced core speed dependency for better yields
Speed (data pin)	400–1066 Mb/s	Provides migration path for higher bus speeds
READ Latency	CL + AL CL = 3, 4, 5, 6, 7	Eliminating one-half clock settings helps speed internal DRAM logic and improves yield
WRITE Latency	READ latency - 1	Improves command bus efficiency
Additive Latency (posted CAS)	AL options 0, 1, 2, 3, 4	Mainly used in server applications to improve command bus efficiency
Termination	DRAM on-die termination (ODT), optional on-motherboard termination	ODT for both memory and controller improves signaling and reduces system cost
Data Strobes	Differential or single-ended	Improves system timing margin by reducing strobe crosstalk
Temperature Ranges	0°C to +85°C 40°C to +95°C 40°C to +85°C 40°C to +105°C	Extended operating ranges for optimum functionality in extreme environments

Saving Space and Power: Continuing Support for DDR2
We believe in supporting technologies that are important to our customers. It’s a strategy we’ve followed to build one of the world’s most extensive memory portfolios, with a full complement of legacy DRAM solutions. It also allows us to support innovative new products like Intel’s “Oak Trail” Atom chipset—a processor designed to deliver low power use and small form factor for the next generation of tablet PCs.

Our transition to 50nm 2Gb DDR2 devices is part of our ongoing commitment to long-term support and continued innovation on mature product lines. These higher-density, 50nm-based components ultimately increase power savings and offer a smaller memory footprint than 1Gb devices.

Given its low-power demands, high capacity, and great performance, DDR2 is well-suited for tablets and many other devices. For more information about our product offerings, see the DDR2 SDRAM Part Catalog, or contact your Micron representative. For more information about the benefits of DDR2, see our comparison of DDR and DDR2 memory technology.

Are there any supply voltage savings with 1.5V DDR2 SDRAM versus 1.55V DDR2 SDRAM?

Yes, the 1.5V DDR2 SDRAM uses about 15–20 percent less current than the 1.55V DDR2 SDRAM.

Are there any timing specification differences between 1.55V DDR2 SDRAM and 1.8V DDR2 SDRAM?

Yes, DLL-controlled output specs require some derating.

Are there any timing specification differences between 1.5V DDR2 SDRAM and 1.8V DDR2 SDRAM?

No.

Can DDR2-1066 be used with two slots?

Using DDR2-1066 with two slots is unrealistic; simulations have not shown acceptable margins.

Can you explain how on-die termination (ODT) affects power consumption?

On-die termination (ODT) power is very application-dependent. ODT is also variable, depending on the setting in the EMR of the DRAM. Use the DDR2 power calculator to determine the values.

In a point-to-point system, ODT would only be active on WRITE cycles, and would not consume power during idle and READ cycles. On-board termination would consume power in these instances. ODT power should be about 2–3 percent of the total DDR2 DRAM power in a typical application.

How much power does the Vref power pin draw?

The Vref pin does not draw any power, only leakage current, which is less than 5µA.

Is DDR2-1066 a JEDEC standard?

Not yet, but it’s in process.

Is the ridge down the middle of the underside of FBGA packages conductive?

No, only designated balls are conductive.

Is VREF allowed to float during self refresh mode?

No, it must be maintained at VDDQ/2.

Should DDR2 SDRAM always have ODT turned on?

It’s not recommended, as the SDRAM reads will lose voltage margin; but technically, it is allowed.

Should the DLL be disabled?

Although in some cases the DRAM may work with the DLL off, this mode of operation is not documented nor supported by JEDEC. Therefore, each DRAM design may behave differently when configured to run with the DLL disabled. Micron does not support or guarantee operation with the DLL disabled. Running the DRAM with the DLL disabled may cause the device to malfunction and/or violate some DRAM output timing specifications.

What is the DDR2 RDQS pin for?

The sole purpose of RDQS is to support the use of a x8-based RDIMM in a x4-based RDIMM system. The RDQS pin enables a x8 DDR2 SDRAM to emulate two x4s.

What is the difference between 1.5V DDR2 SDRAM and 1.55V DDR2 SDRAM?

1.5V DDR2 SDRAM is not backward compatible to 1.8V operating systems, and the 1.55V DDR2 SDRAM is.

What is the maximum clock rate for DDR2 when it’s used with a single-ended DQS?

The answer depends mostly on design implementation. As long as the data setup and holds have 150ps or more of margin and there’s a fast slew rate, a single-ended DQS should be OK.

Will the device run at a slow clock (well under the slowest data sheet speed)?

For a READ operation, the DRAM edge-aligns the strobe(s) with the data. Most controllers sense the strobe to determine where the data window is positioned. This fine strobe/data alignment requires that each DRAM have an internal DLL. The DLL is tuned to operate for a finite frequency range, which is identified in each DRAM data sheet. Running the DRAM outside these specified limits may cause the DLL to become unpredictable. The DRAM is tested to operate within the data sheet limits. Micron does not suggest or guarantee DRAM operation outside these predefined limits.